AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 47

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

In future high performance processors that implement the PowerPC architecture, the preferred instruction
alignment will be that the branch target be the first instruction in a quad word (target address =
0xxxxx_xxx0).
4.3.3
Load hoisting refers to the general technique of increasing the load-to-use distance. Increasing the time
between when a load is executed and the operand is needed reduces stalls waiting for the load to complete
(although a balance must be struck against the increased register pressure). Note that typical MPC7450 load
latencies are longer than in prior microprocessors (see the code in Section 3.1.1.1, “Fetch Alignment
Example”) increasing the benefit of load hoisting.
Some possible load hoisting optimizations include scheduling, moving loads from basic blocks to previous
basic blocks, and moving loads from the bodies of if-then statements or from loops when the analysis
indicates it is safe.
One potential situation that may prevent load hoisting is the possibility of pointer aliasing between a load
and some store operations. Careful analysis of such situations may show that performance would improve
if the code was compiled assuming no aliases between these accesses, with a check and a branch at the
beginning of this code to fix-up code or an alternate version of the code that handles the aliasing case.
The following example shows a function modify_a_b that can be optimized to perform run-time
checking of aliasing.
C Source Code:
Assembly code:
Here is C and assembly code of the function after inserting a run-time alias check. Note that within the first
block, the pointers are only dereferenced once for loads and once for stores.
MOTOROLA
void modify_a_b(int *a, int *b) {
}
lwz 9,0(3)
addi 9,9,5
stw 9,0(3)
lbz 11,3(4)
stw 11,0(4)
lwz 0,0(3)
add 0,0,11
stw 0,0(3)
...
blr
void modify_a_b_smart(int *a, int *b) {
Load Hoisting
MPC7450 RISC Microprocessor Family Software Optimization Guide
*a += 5;
*b &= 0xff;
*a += *b;
...
if (a != b) {
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int aval = *a;
int bval = *b;
aval += 5;
bval &= 0xff;
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Optimizations to Exploit the Memory Hierarchy
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