AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 32

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

FPU Considerations
three IU1 instructions are stuck in the three reservation stations, requiring operands (or until the GIQ or
dispatcher stalls for other reasons).
Table 3-12 shows a case where although two IU1s are blocked, the third makes progress.
Also note that some IU1 instructions take more than one cycle and that some are not fully pipelined. The
most common 2-cycle instructions are sraw and srawi.
The following instructions are not fully pipelined when their record bit is set: extsb, extsh, rlwimi, rlwinm,
rlwnm, slw, and srw. These instructions return GPR data after the first cycle but continue executing into a
second cycle to generate the CR result.
Table 3-15 shows sraw, extsh, and extsh. latency effects. The two sraw instructions both take 2 cycles of
execution, blocking the extsh/extsh. pair from issuing until cycle 3 but allowing the dependent add to
execute in cycle 3 (see Table A-5, footnote 3). Note that extsh. takes two cycles to execute, but that the
dependent subf can pick up the forwarded GPR value after the first cycle of execution (cycle 4) and execute
in cycle 5.
3.5.2
The IU2 has two reservation station entries. Instruction execution is allowed only from the bottom station.
Although mtctr/mtlr instructions are execution serialized, if data is available, their values are forwarded to
the BPU as soon as they are in the bottom reservation station.
Divides, mulhwu, mulhw, and mull are not fully pipelined; they iterate in execution stage 0 and block other
instructions from entering reservation station 0. For example, in Table 3-12, the second multiply issues to
IU2 in cycle 2. Because the first multiply still occupies reservation station 0, the second is issued to
reservation station 1. When the first multiply enters E1, the second moves down to reservation station 0 and
begins execution.
Note that the IU2 takes an extra cycle beyond the latencies listed in Table A-5 to return CR data and finish.
This implies that, as the example in Section 3.3.1, “General Purpose Issue Queue (GIQ),” shows, a 3-cycle
instruction such as mulhw requires a separate finish stage, even though GPR data is still forwarded and used
after three execution cycles. In the previous example, instruction 4 executes in cycle 7, the cycle after the
dependent instruction 2 progressed through its third execution stage.
3.6
The FPU has two reservation station entries. Instruction execution is allowed only from the bottom
reservation station (reservation station 0).
32
FPU Considerations
IU2 Considerations
MPC7450 RISC Microprocessor Family Software Optimization Guide
sraw r1,r20,r21
sraw r2,r20,r22
add r4,r2,r3
extsh r5,r25,
extsh. r6,r26
subf r7,r5,r6
Instruction
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Table 3-15. IU1 Timing Example
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F2
F2
F2
D
D
D
0
D
D
D
1
I
I
I
—
—
—
—
2
E
E
E
E
E
3
I
I
I
—
C
C
C
E
E
4
C
5
E
E
C
C
6
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