AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 5

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
Data cache load hit (integer, vector, float)
IU1 (add, shift, rotate, logical)
IU2: multiply (32-bit)
IU2: divide
FPU: single (add, mul, madd)
FPU: single (divide)
FPU: double (add)
FPU: double (mul, madd)
FPU: double (divide)
VSIU
VCIU
VFPU
VPU
L1 cache size (instruction, data)
L1 cache associativity (instruction, data)
L1 cache line size
L1 cache replacement algorithm
Number of outstanding data cache misses
(load/store)
Additional on-chip cache level
Additional on-chip cache size
Additional on-chip cache associativity
Additional on-chip cache line size
Additional on-chip cache replacement
algorithm
Off-chip cache level
Off-chip cache size
Off-chip cache associativity
Off-chip cache line size/sectors per line
Off-chip cache replacement algorithm
Microprocessor Feature
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
Table 2-1. High-Level Differences (continued)
For More Information On This Product,
L1 Instruction Cache/Data Cache Features
Additional On-Chip Cache Features
Typical Execution Unit Latencies
Go to: www.freescale.com
Off-Chip Cache Support
64B/2, 64B/2, 128B/4 32B/1, 64B/2, 128B/4
512-Kbyte, 1-Mbyte
1 (load or store)
256-Kbyte,
MPC750
2,N/A,2
2-way
None
FIFO
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
19
17
31
1
6
3
3
4
L2
512-Kbyte, 1-Mbyte,
32-Kbyte, 32-Kbyte
8 (any combination
8-way, 8-way
Pseudo-LRU
load/store)
MPC7400
32 bytes
2-Mbyte
2-way
None
FIFO
2,2,2
N/A
N/A
N/A
N/A
19
17
31
1
6
3
3
3
1
3
4
1
High-Level Differences
(2 sectors per line)
1-Mbyte, 2-Mbyte
Pseudo-random
Pseudo-random
64B/2, 128B/4
5 load/1 store
256-Kbyte
MPC7450
64 bytes
8-way
8-way
3,3,4
23
21
35
L2
L3
1
4
5
5
5
1
4
4
2
5