AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 25

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Because a return (bclr) is never paired with this bcl (instruction 0), the MPC7450 takes two special actions
when it recognizes this special form (“bcl 20,31,$+4”):
The instruction address is available for executing a subsequent operation (instruction 2, addi) in cycle 10,
primarily due to the long latency of the execution serialized mflr. However, the data has to be transferred
back to the BPU through the CTR register, which prevents the bcctr to execute until cycle 12, so it’s target
instruction (5) cannot start execution until cycle 17.
Note that it is important that instructions 3 and 4 be a mtctr/bcctr pair rather than a mtlr/bclr pair. A bclr
would try to use the link stack to predict the target address, which would almost certainly be an address
mispredict, which would be even more costly than the 7-cycle branch execution stall for instruction 4 shown
in this example. In addition, an address mispredict would require that the link stack be flushed, which would
mean that bclr instructions that occur later in the program would have to stall rather than use the link stack
address prediction. This would further degrade performance.
3.1.4.3
Computed branches are used in switch statements with enough different entries to warrant a table-lookup
approach (instead of creating a series of if-else tests). The following example shows a typical
implementation of such a switch statement using the CTR register.
Source code in C:
MOTOROLA
Instr.
No.
...
0
1
2
3
4
5
•
•
bcl 20, 31, $+4
mflr r2
addi r2, r2,#constant
mtctr r2
bcctr
add r3, r3, r20
Although the bcl does update the link register as architecturally required, it does not push the value
onto the link stack. Not pairing a return with this bcl prevents the link stack from being corrupted,
which would likely require a later branch mispredict for some later bclr.
Because the branch has the same next instruction address whether it is taken or fall-through, the
branch is forced as a fall-through branch. This avoids a potential branch-taken bubble and saves a
cycle.
switch(x){
Instruction
Computed Branch and Function Pointer Examples
MPC7450 RISC Microprocessor Family Software Optimization Guide
case 0: /* code for case 0. */
case 1: /* code for case 1. */
case 2: /* code for case 2. */
...
default: /* code for default case. */
Freescale Semiconductor, Inc.
Table 3-9. Position-Independent Code Example
F1 F2 BE
F1 F2 —
F1 F2 —
F1 F2 —
0
For More Information On This Product,
break;
break;
break;
F1 F2 —
1
2
Go to: www.freescale.com
—
D
D
D
3
—
C
D
4
I
I
— E0 E1 E2 E3
—
—
5
I
—
—
—
6
—
—
—
7
—
—
—
8
—
—
—
9
10 11 12 13 14 15 16 17
—
—
F
E
Fetch/Branch Considerations
—
— BE
C
C
—
F1 F2
E
C
D
I
E
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