AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 2

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Terminology and Conventions
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This section provides an alphabetical glossary of terms used in this chapter. These definitions review these
commonly used terms and point out specific ways these terms are used in this document.
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Branch prediction—The process of guessing the direction or target of a branch. Branch direction
prediction involves guessing whether a branch will be taken. Target prediction involves guessing
the target address of a bclr branch. The PowerPC architecture defines a means for static branch
prediction as part of the instruction encoding.
Branch resolution—The determination of whether a branch prediction was correct or not. If the
prediction is correct, the instructions following the predicted branch that may have been
speculatively executed can complete (see completion). If the prediction is incorrect, instructions
on the mispredicted path and any results of speculative execution are purged from the pipeline and
fetching continues from the correct path.
Complete—An instruction is in the complete stage after it executes and makes its results available
for the next instruction (see finish). At the end of the complete stage, the instruction is retired from
the completion queue (CQ). When an instruction completes, it is guaranteed that this instruction
and all previous instructions can cause no exceptions.
Dispatch—The dispatch stage decodes instructions supplied by the instruction queue, renames any
source/target operands, determines to which issue queue each non-branch instruction is
dispatched, and determines whether the required space is available in both that issue queue and the
completion queue.
Fall-through folding (branch fall-through)—Removal of a not-taken branch. On the MPC7450,
not-taken branch instructions that do not update LR or CTR can be removed from the instruction
stream if the branch instruction is in IQ3–IQ7.
Fetch—The process of bringing instructions from memory (such as a cache or system memory)
into the instruction queue.
Finish—An executed instruction finishes by signaling the completion queue that execution is
complete and results have been made available to subsequent instructions. For most execution
units, finishing occurs at the end of the last cycle of execution; however, FPU, IU2, and VIU2
instructions finish at the end of a single-cycle finish stage after the last cycle of execution.
Folding (branch folding)—The replacement of a branch instruction and any instructions along the
not-taken path with target instructions when a branch is either taken or predicted as taken.
Issue—The pipeline stage responsible for reading source operands from rename registers and
register files. This stage also assigns and routes instructions to the proper execution unit.
Latency— The number of clock cycles necessary to execute an instruction and make the results of
that execution available to subsequent instructions.
Terminology and Conventions
Because of the differences in the MPC7450, many of these definitions
differ slightly from those used to describe previous processors that
implement the PowerPC architecture, in particular with respect to
dispatch, issue, finishing, retirement, and write back, so reading this
glossary carefully is important.
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
MOTOROLA