AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 33

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Like the IU2, the FPU requires a separate finish stage to return CR and FPSCR data, as shown in Table 3-16.
However, FPR data produced in E4 (the fifth stage) is ready and can be forwarded directly (if needed) to an
instruction entering E0 in the next cycle.
The five-stage scalar FPU pipeline has a 5-cycle latency. However, when the pipeline contains instructions
in stages E0–E3, the pipeline stalls and does not allow a new instruction to start in E0 on the following cycle.
This bubble limits maximum FPU throughput to four instructions every five cycles, as the following code
example shows:
xxxxxx00
xxxxxx04
xxxxxx08
xxxxxx0C
xxxxxx10
xxxxxx14
xxxxxx18
xxxxxx1C
xxxxxx20
Table 3-16 shows the timing for this sequence.
The FPU is also constrained by the number of FPSCR rename registers. The MPC7450 supports four
outstanding FPSCR updates. An FPSCR is allocated in the E3 FPU stage and is deallocated at completion.
If no FPSCR rename is available, the FPU pipeline stalls. A fully pipelined case such as that in Table 3-16
is not affected, but if something blocks completion it can become a bottleneck. Consider the following code
example:
xxxxxx00l
xxxxxx04
xxxxxx08
xxxxxx0C
xxxxxx10
xxxxxx14
xxxxxx18
xxxxxx1C
xxxxxx20
MOTOROLA
fadd
fadd
fadd
fadd
fadd
fadd
fadd
fadd
fadd
Instruction
F2
F2
F2
F2
F1
—
—
—
D
0
MPC7450 RISC Microprocessor Family Software Optimization Guide
F2
—
—
—
—
—
—
D
fadd f10,f20,f21
fadd f11,f20,f22
fadd f12,f20,f23
fadd f13,f20,f24
fadd f14,f20,f25
fadd f15,f20,f26
fadd f16,f20,f27
fadd f17,f20,f28
fadd f18,f20,f29
1
fdu f3,0x8(r9)
fadd f11,f20,f22
fadd f12,f20,f23
fadd f13,f20,f24
fadd f14,f20,f25
fadd f15,f20,f26
fadd f16,f20,f27
fadd f17,f20,f28
fadd f18,f20,f29
I
E0
—
—
—
—
—
—
D
2
I
Freescale Semiconductor, Inc.
For More Information On This Product,
E1
E0
—
—
—
—
—
D
3
I
Table 3-16. FPU Timing Example
E2
E1
E0
—
—
—
—
D
4
I
Go to: www.freescale.com
E3
E2
E1
E0
—
—
—
D
5
I
E4
E3
E2
E1
—
—
—
—
D
6
E4
E3
E2
E0
—
—
—
7
F
I
E4
E3
E1
E0
—
C
F
D
8
I
E4
E2
E1
E0
C
D
9
F
I
E3
E2
E1
E0
10
C
F
I
E4
E3
E2
E1
11
—
C
12
E4
E3
E2
E0
F
FPU Considerations
E4
E3
E1
13
C
F
E4
E2
14
C
F
E3
15
C
F
E4
16
C
33