AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 28

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Dispatch Considerations
3.2.2
The MPC7450 splits load/store multiple instructions (lmw and stmw) and strings (lsw and stsw) into
micro-operations at the dispatch point. The processor can dispatch only one micro-operation per cycle,
which does not use the dispatcher to its full advantage.
Using load/store multiple instructions is best restricted to cases where minimizing code size is critical or
where there are no other available instructions to be scheduled, such that the under-utilization of the
dispatcher is not a consideration.
3.2.2.1
Consider the following assembly instruction sequence:
0
1
2
3
4
5
6
7
The load multiple instruction specified with register 25 loads registers 25–31. The MPC7450 splits this
instruction into seven micro-operations at dispatch, after which the lmw executes as multiple operations, as
Table 3-11 shows.
28
Instr.
No.
0–0
0–1
0–2
0–3
0–4
0–5
0–6
1
2
3
4
5
6
7
lmw
addi r25,r25,0x01
addi r26,r26,0x01
addi r27,r27,0x01
addi r28,r28,0x01
addi r29,r29,0x01
addi r30,r30,0x01
addi r31,r31,0x01
lmw r25,0x00(r1)
lmw r26,0x04(r1)
lmw r27,0x08(r1)
lmw r28,0x0C(r1)
lmw r29,0x10(r1)
lmw r30,0x14(r1)
lmw r31,0x1C(r1)
addi r25,r25,0x01
addi r26,r26,0x01
addi r27,r27,0x01
addi r28,r28,0x01
addi r29,r29,0x01
addi r30,r30,0x01
addi r31,r31,0x01
Instruction
r25,0x00(r1)
Dispatching Load/Store Strings and Multiples
Example of Load/Store Multiple Micro-Operation Generation
Table 3-11. Load/Store Multiple Micro-Operation Generation Example
MPC7450 RISC Microprocessor Family Software Optimization Guide
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