AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 39

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

If a load misses in the L1 data cache and in the L2 data cache, critical data forwarding occurs, followed
shortly by the rest of the line. The following example shows that the load L3 cache hit latency is effectively
33 cycles.
The following L3 parameters are assumed for the example in Table 3-26:
Note that the LMQ0 entry for the load remained allocated for four cycles after the critical data arrived in
cycle 32. This is because with a 4:1 DDR SRAM, there is a 4-cycle gap between critical data and full line
data, and the LMQ entry is only deallocated when the full line has returned.
If a load/store miss aliases to the same line as a previously outstanding miss, the LSU halts new access until
this stall condition is resolved. The following example contains a series of loads, where the data starts in the
L3 cache, with the L3 cache configured similarly to the example in Table 3-26.
MOTOROLA
lwz r4,0x0(r9)
add r5,r4,r3
Instr.
•
•
•
No.
Instruction
0
1
2
3
4
5
0
1
2
3
4
5
DDR SRAM at 4:1 L3 bus ratio
L3 clock sample point is 5 clocks
L3 Processor-clock sample point is 0 clocks
lwz r4,0x0(r9)
add r5,r4,r3
Instruction
lwz r3,0x0(r9)
add r4,r3,r20
lwz r5,0x4(r9)
add r6,r5,r4
lwz r7,0x20(r9)
lwz r3,0x0(r9)
add r4,r3,r20
lwz r5,0x4(r9)
add r6,r5,r4
lwz r7,0x20(r9)
add r8,r7,r6
add r8,r7,r6
Instruction
MPC7450 RISC Microprocessor Family Software Optimization Guide
Table 3-26. Data Cache Miss, L2 Cache Miss, L3 Cache Hit Timing
E0
0
Table 3-25. Data Cache Miss, L2 Cache Hit Timing
Freescale Semiconductor, Inc.
E0
—
0
37–39
For More Information On This Product,
Table 3-27. Load Miss Line Alias Example
E0
E1
E0
D
D
0
I
I
E1
1
E1
—
1
Go to: www.freescale.com
E1
E0
E2
E1
40
1
I
I
Miss
2
Miss
Miss
Miss
—
2
E1
E0
41
C
2
E
LMQ0
3–31
LMQ0
LMQ0
3–31
LMQ0
E1
E0
42
3–7
Cycle Number
C
—
LMQ0/E2
32
LMQ0/E2
43–61
LMQ0
LMQ0/E2
E1
E0
32
—
8
LMQ0/C
33
LMQ0/E2 LMQ0/C
E
LMQ0/C
E1
E0
33
62
E
C
9
E
Load/Store Unit (LSU)
LMQ0
34
C
LMQ0
E1
E0
34
63
C
E
10
C
35–36
LMQ0
35–36
LMQ0
LMQ0
E1
E0
64
C
39