AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 41

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

3.7.7
The MPC7450 VTE engine is similar to that on the MPC7400 but can only initiate an access every three
cycles rather than two. However, due to miss-handling differences described in Section 3.7.6, “Load Miss
Pipeline,” the engine may fall behind and conflict with the processor work. Therefore, retuning the dst may
be necessary to optimize MPC7450 performance as compared to the MPC7400.
Also, note the information on hardware prefetching in Section 3.8.4, “Hardware Prefetching.” Although
hardware prefetching is useful for many general-purpose applications, it may not be the best choice when
active prefetch control through software is attempted. Hardware prefetching can sometimes interfere with
the dst engine’s attempt to keep the bus busy with specific prefetch transactions, especially for dst strides
larger than one cache block or transient dst operations. Experimentation is encouraged, but in this instance
the best solution may be to disable hardware prefetching.
3.8
The three-level cache implementation affects instruction fetching, and the loading and storing of source and
destination operands, as described in the following sections.
3.8.1
The MPC7450 follows the PowerPC architecture in ordering all cache-inhibited guarded loads with respect
to other cache-inhibited guarded loads. It also orders cache-inhibited guarded stores with respect to other
cache-inhibited guarded stores and all stores with respect to earlier loads. Cache-inhibited guarded loads are
normally only ordered with previous cache-inhibited guarded stores if they are to overlapping addresses.
The eieio instruction forces ordering of cache-inhibited guarded loads with previous cache-inhibited
guarded stores to different addresses. The best performance of sequences of cache-inhibited and guarded
ordered accesses is gained when stores are grouped and then a single eieio instruction is used to form a
barrier between the group of stores and any subsequent load.
3.8.2
The unified 256-Kbyte on-chip L2 cache has 8-way set associativity and 64-byte lines (with two
sectors/lines). This implies 4096 lines (256 K/64) and 512 sets (256 Kbyte/64/8). Each line has two sectors
with one tag per line but separate valid and dirty bits for each sector. Because of the sectoring, code uses
more of the L2 storage if the spatial locality is characterized by the use of the adjacent 32-byte line.
A load that misses in the L1 but hits in the L2 causes a full line reload. Its latency is ideally nine cycles (six
more than for an L1 hit) assuming no other higher priority L2 traffic. See Table 3-25.
An access missing in the L2 goes to the L3 or main memory bus to fetch the needed 32-byte sector.
The L2 cache uses a pseudo-random replacement algorithm. With 8-way set associativity, a miss randomly
replaces one of eight ways. This works well for smaller working set sizes, but for working set sizes close to
the size of the cache, the hit rate is not quite as good. Imagine a 64-Kbyte array structure and a byte striding
access pattern that loops over the array several times. The access of the first 32 Kbytes (256-Kbyte/8-ways)
will miss and load correctly, but the second 32 Kbytes has a one in eight chance per set of thrashing with an
index of the first 32 Kbytes. This means that the first pass will probabilistically leave 93.75 percent of the
64-Kbyte structure in the L2 cache, and a second pass through the 64-Kbyte will probabilistically leave
99.8 percent of the 64-Kbyte structure in the L2 cache.
MOTOROLA
Memory Subsystem (MSS)
DST Instructions and the Vector Touch Engine (VTE)
I/O Access Ordering
L2 Cache Effects
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
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Memory Subsystem (MSS)
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