AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 3

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
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Pipeline—In the context of instruction timing, the term ‘pipeline’ refers to the interconnection of
the stages. The events necessary to process an instruction are broken into several cycle-length tasks
to allow work to be performed on several instructions simultaneously—analogous to an assembly
line. As an instruction is processed, it passes from one stage to the next. When it does, the stage
becomes available for the next instruction.
Although an individual instruction can take many cycles to make results available (see latency),
pipelining makes it possible to overlap processing so that the throughput (number of instructions
processed per cycle) is greater than if pipelining were not implemented.
Program order—The order of instructions in an executing program. More specifically, this term is
used to refer to the original order in which program instructions are fetched into the instruction
queue from the cache.
Rename registers—Temporary buffers for holding results of instructions that have finished
execution but have not completed.
Reservation station—A buffer between the issue and execute stages that allows instructions to be
issued even though the results of other instructions on which the issued instruction may depend are
not available.
Retirement—Removal of a completed instruction from the CQ.
Speculative instruction—Any instruction that is currently behind an unresolved older branch.
Stage—A stage is an element in the pipeline where specific actions are performed, such as
decoding the instruction, performing an arithmetic operation, or writing back the results. Typically,
the latency of a stage is one processor clock cycle. Some events, such as dispatch, writeback, and
completion, happen instantaneously and may be thought to occur at the end of a stage.
An instruction can spend multiple cycles in one stage. An integer multiply, for example, takes
multiple cycles in the execute stage. When this occurs, subsequent instructions may stall.
An instruction can also occupy more than one stage simultaneously, especially in the sense that a
stage can be viewed as a physical resource—for example, when instructions are dispatched they
are assigned a place in the CQ at the same time they are passed to the issue queues.
Stall—An occurrence when an instruction cannot proceed to the next stage.
Superscalar—A superscalar processor is one that can issue multiple instructions concurrently from
a conventional linear instruction stream. In a superscalar implementation, multiple instructions can
be in the execute stage at the same time.
Throughput—The number of instructions that are processed per cycle. For example, a series of
mulli instructions have a throughput of one instruction per clock cycle.
Write-back—Write-back (in the context of instruction handling) occurs when a result is written
into the architecture-defined registers (typically the GPRs, FPRs, and VRs). On the MPC7450,
write-back occurs in the clock cycle after the completion stage. Results in the write-back buffer
cannot be flushed. If an exception occurs, results from previous instructions must write back
before the exception is taken.
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Terminology and Conventions
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