mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 17

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Table 8:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
128mb_mobile_ddr_sdram_t35m__2.fm - Rev. B 06/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
CS is HIGH between valid commands; Address inputs are switching
every two clock cycles; Data bus inputs are stable
Precharge power-down standby current: All banks idle; CKE is LOW;
CS is HIGH;
switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle;
CKE = HIGH; CS = HIGH;
are switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH;
Data bus inputs are stable
Active power-down standby current: Clock stopped; One bank
active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: One bank active; CKE = HIGH;
CS = HIGH;
Data bus inputs are stable
Active nonpower-down standby: Clock stopped; One bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control
inputs are switching; Data bus inputs are stable
Operating burst read: One bank active; BL = 4; CL = 3;
t
are switching every two clock cycles; 50 percent data changing each
burst
Operating burst write: One bank active; BL = 4;
Continuous WRITE bursts; Address inputs are switching; 50 percent
data changing each burst
Auto refresh: Burst refresh; CKE = HIGH; Address
and control inputs are switching; Data bus inputs
are stable
Deep power-down current: Address and control pins are stable; Data
bus inputs are stable
RC =
CK =
t
t
RC (MIN);
CK (MIN); Continuous READ bursts; I
t
t
t
CK =
CK =
CK =
I
Notes: 1–5 apply to all parameters/conditions in this table; notes appear on page 18;
V
DD
DD
t
t
t
CK =
t
/V
CK (MIN); Address and control inputs are switching;
CK (MIN); Address and control inputs are switching;
CK (MIN); Address and control inputs are
Specifications and Conditions (x32)
DD
Q = 1.70–1.95V
t
CK (MIN); CKE is HIGH;
t
CK =
t
CK (MIN); Address and control inputs
OUT
= 0mA; Address inputs
t
CK =
t
t
RFC
RFC =
t
CK (MIN);
=
tRFCmin
t
REFI
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
Symbol
I
I
I
I
I
I
DD
I
DD
I
I
I
I
DD
DD
DD
DD
DD
DD
I
DD
DD
I
I
DD
DD
DD
DD
2NS
3NS
2PS
3PS
4W
2N
3N
4R
5A
2P
3P
0
5
8
200
200
110
110
70
20
15
25
20
95
-5
3
3
8
10
200
200
105
105
-54
Electrical Specifications
60
17
12
22
17
92
3
3
6
Max
©2007 Micron Technology, Inc. All rights reserved.
200
200
100
100
50
15
10
20
15
90
-6
3
3
5
10
-75
200
200
40
12
15
10
90
90
85
8
3
3
3
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
Preliminary
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6