mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 22

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
128mb_mobile_ddr_sdram_t35m__2.fm - Rev. B 06/08 EN
10. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If slew
11. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and
12. These parameters guarantee device timing but are not tested on each device.
13. The valid data window is derived by achieving other specifications:
14.
15.
16.
17. Fast command/address input slew rate
18. The refresh period equals 64ms. This equates to an average refresh rate of 15.6µs.
19. This is not a device limit. The device will operate with a negative value, but system perfor-
20. The maximum limit for this parameter is not a device limit. The device will operate with a
21. At least one clock cycle is required during
22. Clock must be toggled a minimum of two times during the
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point at
6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for all
7. Timing tests may use a V
8.
9. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8]. For
ence load to system environment. Specifications are correlated to production test condi-
tions (generally a coaxial transmission line terminated at the tester electronics). For the
half-strength driver with a nominal 10pF load, parameters
in the same range. However, these parameters are not subject to production test but are
estimated by design/characterization. Use of IBIS or other simulation tools for system design
validation is suggested.
which CK and CK# cross; the input reference voltage level for signals other than CK/CK# is
V
parameters. All AC timings assume an input slew rate of 1 V/ns.
ing is still referenced to V
erence voltage level is V
t
higher integer.
x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
rate exceeds 4 V/ns, functionality is uncertain.
addresses) are measured between V
V
t
cycle and a practical data valid window can be derived. The clock is allowed a maximum
duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55
ratio.
t
inputs, collectively.
t
These parameters are not referenced to a specific voltage level, but specify when the device
output is no longer driving (
t
V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated:
per each 100 mV/ns reduction in slew rate from the 0.5 V/ns.
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain.
mance could be degraded due to bus turnaround.
greater value for this parameter, but system performance (bus turnaround) will degrade
accordingly.
DAL = (
QH (
HP (MIN) is the lesser of
HZ and
HZ (MAX) will prevail over
DD
IL
I/O
(
AC
Q/2.
Full drive strength
t
) for falling input signals.
HP -
z
t
0
t
WR/
LZ transitions occur in the same access time windows as valid data transitions.
= 50
t
QHS). The data valid window derates directly proportional with the clock duty
t
CK) + (
t
RP/
20pF
t
DD
IL
CK): for each term, if not already an integer, round to the next
t
CL (MIN) and
-to-V
DD
Q/2.
t
Q/2 or to the crossing point for CK/CK#. The output timing ref-
t
DQSCK (MAX) +
22
HZ) or begins driving (
I/O
IH
One-half drive strength
swing of up to 1.5V in the test environment, but input tim-
IL
z
0
(
DC
= 50
≥
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
128Mb: x16, x32 Mobile DDR SDRAM
CH (MIN) actually applied to the device CK and CK#
1 V/ns. Slow command/address input slew rate
) to V
t
WR time when in auto precharge mode.
t
RPST (MAX) condition.
IH
(
AC
) for rising input signals and V
10pF
t
LZ).
Electrical Specifications
t
t
AC and
XSR period.
t
IH has 0ps added, therefore, it
©2007 Micron Technology, Inc. All rights reserved.
t
IS has an additional 50ps
t
t
QH are expected to be
HP (
t
CK/2),
t
Preliminary
DQSQ, and
IH
(
DC
) to
≥
0.5