mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 41

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Register Definition
Mode Registers
Standard Mode Register
Figure 16:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Standard Mode Register Definition
Notes:
1. The integer n is equal to the most significant address bit.
The mode registers are used to define the specific mode of operation of the Mobile DDR
SDRAM. Two mode registers are used to specify the operational characteristics of the
device: standard mode register and extended mode register.
The standard mode register bit definition enables the selection of burst length, burst
type, CAS latency, and operating mode, as shown in Figure 16 on page 41. Reserved
states should not be used as it may result in setting the device into an unknown state or
cause incompatibility with future versions of Mobile DDR SDRAMs. The standard mode
register is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again, the device
goes into deep power-down mode, or the device loses power.
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait
quent operation. Violating any of these requirements will result in unspecified opera-
tion.
Mn
0
–
...
M10
M
0
–
n + 2
0
0
1
1
M9
0
–
M
M8
n + 1
n+2
0
1
0
1
0
–
BA1
0
M7
n+1
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
0
BA0
M6
0
0
0
0
1
1
1
1
Operating Mode
Normal operation
All other states reserved
n
An ...
Operating Mode
M5
...
0
0
1
1
0
0
1
1
10
A10
M4
41
0
1
0
1
0
1
0
1
9
A9
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
A8
2
3
7
A7 A6 A5 A4 A3
CAS Latency BT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
6
5
4
M3
0
1
3
Burst Length
M2
2
t
0
0
0
0
1
1
1
1
A2 A1 A0
MRD before initiating the subse-
Interleaved
Burst Type
Sequential
M1
1
0
0
1
1
0
0
1
1
0
M0
0
1
0
1
0
1
0
1
Standard mode register (Mx)
Reserved
Reserved
Reserved
Reserved
M3 = 0
Address bus
©2007 Micron Technology, Inc. All rights reserved.
16
Burst Length
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
16
2
4
8
Operations
Preliminary