mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 70

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mt46h8m16lfcf-75-it

Manufacturer Part Number
mt46h8m16lfcf-75-it
Description
128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
Manufacturer
Micron Semiconductor Products
Datasheet
Figure 41:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Interrupting
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. PRE = PRECHARGE.
2.
3. D
4. An interrupted burst of 8 is shown; two data elements are written.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T4 and T4n to register DM.
t
WR is referenced from the first positive CK edge after the last data-in pair.
D
b
IN
IN
NOP
b = data-in for column b.
T1
D
b
IN
3
b + 1
D
D
b
IN
IN
T1n
b + 1
D
IN
b + 1
D
IN
NOP
T2
T2n
70
t
WR
T3
NOP
2
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
(a or all)
PRE
T4
Bank
1
Don’t Care
T4n
T5
NOP
©2007 Micron Technology, Inc. All rights reserved.
Timing Diagrams
Transitioning Data
T6
NOP
Preliminary

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