mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 81

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Figure 51:
Stopping the External Clock
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
CKE
CK#
CK
All banks idle with no
activity on the data bus
Deep Power-Down
Notes:
NOP
T0
1. Clock must be stable prior to CKE going HIGH.
2. DPD = deep power-down.
3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required.
One method of controlling the power efficiency in applications is to throttle the clock
that controls the DDR SDRAM. The clock may be controlled in two ways:
• Change the clock frequency
• Stop the clock.
The Mobile DDR SDRAM enables the clock to change frequency during operation only if
all the timing parameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be
completed before entering clock stop mode; this includes the following timings:
t
be complete as defined in the “READs” section on page 49 and the “WRITEs” section on
page 60.
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued. Figure 52 on page 82 illus-
trates the clock stop mode.
RP,
t
RFC,
t
DPD
IS
T1
Enter deep power-down mode
t
MRD,
2
t
WR, and
T2
(
(
(
(
)
(
)
t
)
)
)
(
(
CKE
(
)
(
)
(
)
)
)
t
RPST. In addition, any READ or WRITE burst in progress must
81
Ta0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
Ta1
NOP
Exit deep power-down mode
T = 200μs
Ta2
NOP
©2007 Micron Technology, Inc. All rights reserved.
Timing Diagrams
Don’t Care
Ta3
PRE
Preliminary
3
t
RCD,