mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 47

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Figure 19:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
BA0, BA1
Address
DQS
CK#
DQ
CK
PRE
T0
SRR Timing
1
Notes:
t RP
NOP
T1
2. NOP or DESELECT commands are required between LMR and READ command (
3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown as
4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register.
5. The second bit of the data-out burst is a “Don’t Care.”
1. All banks must be idle prior to status register read.
between READ and next VALID command (
an example only.
BA0 = 1
BA1 = 0
LMR
0
T2
t SRR
NOP
T3
2
47
READ
T4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
t
SRC).
NOP
T5
CL = 3
3
t SRC
NOP
T6
©2007 Micron Technology, Inc. All rights reserved.
T7
NOP
out
SRR
4
Operations
Don’t
care
t
SRR) and
Preliminary
5
Don’t Care
Valid
T8