mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 56

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mt46h8m16lfcf-75-it

Manufacturer Part Number
mt46h8m16lfcf-75-it
Description
128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
Manufacturer
Micron Semiconductor Products
Datasheet
Figure 27:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
Command
Address
Address
READ-to-PRECHARGE
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
Notes:
Banka,
Banka,
READ
Col n
READ
1. D
2. BL = 4, or an interrupted burst of 8 or 16.
3. Shown with nominal
4. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out.
5. A READ command with auto precharge enabled, provided
6. PRE = PRECHARGE command; ACT = ACTIVE command.
Col n
T0
T0
precharge to be performed at x number of clock cycles after the READ command, where x =
BL/2.
OUT
n = data-out from column n.
CL = 2
NOP
NOP
T1
T1
CL = 3
T1n
T1n
t
AC,
D
(a or all)
(a or all)
Banka,
Banka,
OUT
n
T2
PRE
T2
PRE
t
DQSCK, and
56
D
n + 1
T2n
T2n
OUT
D
OUT
n
D
n + 2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
T3
NOP
128Mb: x16, x32 Mobile DDR SDRAM
T3
NOP
DQSQ.
OUT
t RP
D
n + 1
t RP
Don’t Care
OUT
T3n
D
n + 3
T3n
OUT
D
n + 2
OUT
T4
NOP
T4
NOP
t
RAS (MIN) is met, would cause a
D
n + 3
OUT
Transitioning Data
©2007 Micron Technology, Inc. All rights reserved.
Banka,
Banka,
Timing Diagrams
T5
T5
ACT
Row
ACT
Row
Preliminary

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