mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 39
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mt46h8m16lfcf-75-it
Manufacturer Part Number
mt46h8m16lfcf-75-it
Description
128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46H8M16LFCF-75-IT.pdf
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Initialization
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
10. Issue NOP or DESELECT commands for at least
1. The core power (V
2. When power supply voltages are stable and the CKE has been driven HIGH, it is safe
3. When the clock is stable, a 200µs minimum delay is required by the Mobile DDR
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at
7. Using the LOAD MODE REGISTER command, load the standard mode register as
8. Issue NOP or DESELECT commands for at least
9. Using the LOAD MODE REGISTER command, load the extended mode register to the
The following sections provide detailed information covering device initialization,
register definition, and device operation.
Prior to normal operation, Mobile DDR SDRAMs must be powered up and initialized in a
predefined manner. Initialization procedures, other than those specified, will result in
undefined operation.
If there is an interruption to the device power, the initialization routine must be followed
to ensure proper functionality of the Mobile DDR SDRAM.
To properly initialize the Mobile DDR SDRAM, this sequence must be followed:
After steps 1 through 10 are completed, the Mobile DDR SDRAM has been properly
initialized and is ready to receive any valid command.
recommended that V
never exceed V
to apply the clock.
SDRAM prior to applying an executable command. During this time, NOP or DESE-
LECT commands must be issued on the command bus.
least
LECT commands for at least
issued. Typically, both of these commands are issued at this stage as described above.
desired.
desired operating modes. Note that the sequence in which the standard and extended
mode registers are programmed is not critical.
t
RFC time. Issue a second AUTO REFRESH command followed by NOP or DESE-
DD
. Assert and hold CKE HIGH.
DD
) and I/O power (V
DD
and V
39
t
RFC time. Two AUTO REFRESH commands must be
DD
Q be from the same power source or V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
DD
Q) must be brought up simultaneously. It is
t
t
t
RP time.
MRD time.
MRD time.
©2007 Micron Technology, Inc. All rights reserved.
Operations
Preliminary
DD
Q must
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