mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 77

• Manufacturer Part Number: mt46h8m16lfcf-75-it
• Description: 128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
• Manufacturer: Micron Semiconductor Products

Auto Refresh
Figure 47:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
BA0, BA1
Address
DQS
DQ
DM
CKE
CK#
A10
CK
5
5
1
5
Auto Refresh Mode
t
t
IS
IS
NOP 2
T0
t
IH
t
Notes:
IH
Bank(s)
One bank
All banks
PRE
T1
1. PRE = PRECHARGE; AR = AUTO REFRESH.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at
3. NOP or COMMAND INHIBIT are the only commands supported until after
4. Bank x at T1 is “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-
Auto refresh mode is used during normal operation of the Mobile DDR SDRAM and is
analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. The AUTO
REFRESH command is nonpersistent and must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command.
For improved efficiency in scheduling and switching between tasks, some flexibility in
the absolute refresh interval is provided. The auto refresh period begins when the AUTO
REFRESH command is registered and ends
Although it is not a JEDEC requirement, CKE must be active (HIGH) during the auto
refresh period to provide support for future functional features. The auto refresh period
begins when the AUTO REFRESH command is registered and ends
4
t
CK
these times. CKE must be active during clock positive transitions.
must be active during clock positive transitions.
bank is active (for example, must precharge all active banks).
back AUTO REFRESH commands.
NOP
Valid
T2
2
t
CH
t
RP
t
CL
NOP
T3
2
T4
AR
77
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t
RFC
NOP
Ta0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
2, 3
t
RFC later.
Ta1
AR
6
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NOP
Valid
Tb0
2, 3
©2007 Micron Technology, Inc. All rights reserved.
t
RFC
Timing Diagrams
t
NOP 2
Tb1
6
RFC later.
t
RFC time; CKE
Don’t Care
ACTIVE
Preliminary
Bank
Tb2
Row
Row