ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 10

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
2–2
Arria GX Device Handbook, Volume 1
Figure 2–1
architecture divided into four channels.
Figure 2–1. Transceiver Block
Each transceiver block has:
■
■
■
■
Four transceiver channels with dedicated physical coding sublayer
(PCS) and physical media attachment (PMA) circuitry
One transmitter PLL that takes in a reference clock and generates
high-speed serial clock depending on the functional mode
Four receiver PLLs and clock recovery unit (CRU) to recover clock
and data from the received serial data stream
State machines and other logic to implement special features
required to support each protocol
Logic Array
Arria GX
shows a high-level diagram of the transceiver block
Transceiver Block
(PLLs, State Machines,
Supporting Blocks
Programming)
Channel 1
Channel 0
Channel 2
Channel 3
Altera Corporation
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
May 2008