ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 142

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Configuration and Testing
3–2
Arria GX Device Handbook, Volume 1
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
PULSE_NCONFIG
Table 3–1. Arria GX JTAG Instructions (Part 1 of 2)
JTAG Instruction
(1)
(1)
(1)
Instruction Code
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 0001
1
—
Arria GX, Stratix
Cyclone
devices in a JTAG chain. All of these devices have the same JTAG
controller. If any of the Stratix, Arria GX, Cyclone, and
Cyclone II devices are in the 18th or further position, they will
fail configuration. This does not affect the functionality of the
SignalTap II embedded logic analyzer.
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation and permits an
initial data pattern to be output at the device pins. Also used by
the SignalTap II embedded logic analyzer.
Allows external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing
test results at the input pins.
Places the 1-bit bypass register between the
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation.
Selects the 32-bit
the
shifted out of
Selects the
TDO
Places the 1-bit bypass register between the
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation, while tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation while holding I/O pins to a state defined by
the data in the boundary-scan register.
Used when configuring an Arria GX device via the JTAG port
with a USB-Blaster™, MasterBlaster™, ByteBlasterMV™, or
ByteBlaster II download cable, or when using a .jam or .jbc via
an embedded processor or JRunner
Emulates pulsing the
reconfiguration even though the physical pin is unaffected.
®
TDI
, allowing
II, and Cyclone devices must be within the first 17
and
IDCODE
®
TDO
TDO
IDCODE
, Stratix II, Stratix GX, Stratix II GX,
.
USERCODE
pins, allowing the
register and places it between
nCONFIG
to be serially shifted out of
Description
register and places it between
pin low to trigger
USERCODE
TM
.
TDI
TDI
TDI
Altera Corporation
to be serially
and
and
and
TDO
TDI
TDO
TDO
TDO
.
May 2008
and