ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 162

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Operating Conditions
4–8
Arria GX Device Handbook, Volume 1
Note to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) Time for which the CDR needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is
(11) Time taken to recover valid data from GXB after the rx_locktodata signal is asserted in manual mode. Measurement
(12) Time taken to recover valid data from GXB after the rx_freqlocked signal goes high in automatic mode.
(13) This is applicable only to PCI Express (PIPE) ×4 and XAUI ×4 mode.
(14) Time taken to lock TX PLL from gxb_powerdown deassertion.
(15) The 1.2 V RX VICM settings is intended for DC-coupled LVDS links.
PCS
Interface speed per
mode
Digital Reset Pulse
Width
Table 4–6. Arria GX Transceiver Block AC Specification (Part 4 of 4)
Symbol / Description
Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver
share the same clock source.
The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard.
The fixedclk is used in PIPE mode receiver detect circuitry.
The device cannot tolerate prolonged operation at this absolute maximum.
The rate matcher supports only up to ± 300 PPM for PIPE mode and ± 100 PPM for GIGE mode.
This parameter is measured by embedding the run length data in a PRBS sequence.
Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode).
Time taken for rx_pll_locked to go high from rx_analogreset deassertion. Refer to
Refer to protocol characterization documents for lock times specific to the protocols.
asserted in manual mode. Refer to
results are based on PRBS31, for native data rates only. Refer to
Measurement results are based on PRBS31, for native data rates only. Refer to
Table
4–6:
Figure 4–1
shows the lock time parameters in automatic mode.
1
Conditions
Figure
LTD = Lock to data
LTR = Lock to reference clock
shows the lock time parameters in manual mode.
4–1.
-6 Speed Grade Commercial and
Minimum is 2 parallel clock cycles
Min
25
Figure
4–1.
Industrial
Figure
Typ
4–2.
Figure
156.25
Altera Corporation
Max
4–1.
Figure 4–2
May 2008
MHz
Unit