ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 12

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
2–4
Arria GX Device Handbook, Volume 1
You can configure the transceiver channels to the desired functional
modes usingthe ALT2GXB MegaCore instance in the Quartus
MegaWizard
Depending on the selected functional mode, the Quartus II software
automatically configures the transceiver channels to employ a subset of
the sub-blocks listed above.
Transmitter Path
This section describes the data path through the Arria GX transmitter. The
sub-blocks are described in order from the PLD-transmitter parallel
interface to the serial transmitter buffer.
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a
reference clock and synthesizes two clocks: a high-speed serial clock to
serialize the data and a low-speed parallel clock to clock the transmitter
digital logic (PCS).
The CMU is further divided into three sub-blocks:
■
■
■
One transmitter PLL
One central clock divider block
Four local clock divider blocks (one per channel)
®
Plug-in Manager for the Arria GX device family.
Altera Corporation
®
II
May 2008