ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 287

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Notes to
(1)
(2)
(3)
% spread
t
t
t
t
f
f
f
t
f
f
f
t
f
t
t
P L L _ P S E R R
ARESET
ARESET_RECONFIG
RECONFIGWAIT
IN
INPFD
INDUTY
INJITTER
VCO
OUT
OUT_EXT
CONFIGPLL
CLBW
LOCK
PLL_PSERR
Table 4–116. Enhanced PLL Specifications (Part 2 of 2)
Table 4–117. Fast PLL Specifications (Part 1 of 2)
This is limited by the I/O f
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
250 ps for ≥ 100 MHz outclk. 25 mUI for <100 MHz outclk.
Name
Name
Table
4–116:
Input clock frequency
Input frequency to the PFD
Input clock duty cycle
Input clock jitter tolerance in terms of period
jitter. Bandwidth
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 0.2 MHz
Upper VCO frequency range
Lower VCO frequency range
PLL output frequency to
PLL output frequency to LVDS or DPA clock
PLL clock output frequency to regular I/O
Time required to reconfigure scan chains for
fast PLLs
PLL closed-loop bandwidth
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
Accuracy of PLL phase shift
Percent down spread for a given clock
frequency
Accuracy of PLL phase shift
Minimum pulse width on
Minimum pulse width on the
signal when using PLL reconfiguration.
Reset the PLL after
The time required for the wait after the
reconfiguration is done and the areset is
applied.
MAX
.
Description
Description
≤
2 MHz
scandone
GCLK
areset
areset
or
goes high.
RCLK
signal.
4.6875
4.6875
16.08
16.08
Min
500
0.4
1.16
Min
300
150
150
10
40
Arria GX Device Handbook, Volume 1
DC and Switching Characteristics
75/f
0.03
Typ
0.5
SCANCLK
Typ
0.5
1.0
5
Max
±30
0.6
Max
640
500
840
420
550
840
±30
2
(1)
60
28
1
ns (p-p)
ns (p-p)
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ns
ns
us
%
ms
4–133
ns
ps
%