ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 280

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Duty Cycle Distortion
4–126
Arria GX Device Handbook, Volume 1
Tables 4–108
derivation for different I/O standards on Arria GX devices. Examples are
also provided that show how to calculate DCD as a percentage.
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 125 ps (see
clock period T is:
To calculate the DCD as a percentage:
Therefore, the DCD percentage for the output clock at 267 MHz is from
46.66% to 53.33%.
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
Table 4–108. Maximum DCD for Non-DDIO Output on Row I/O Pins
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
(T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high
boundary)
Row I/O Output Standard
through
Table
4–113
4–109). If the clock frequency is 267 MHz, the
show the maximum DCD in absolution
Maximum DCD (ps) for Non-DDIO Output
-6 Speed Grade
275
155
135
180
195
145
125
100
115
85
80
Altera Corporation
Unit
May 2008
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps