ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 123

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Table 2–24
strength control.
Note to
(1)
Open-Drain Output
Arria GX devices provide an optional open-drain (equivalent to an open
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (for example, interrupt and
write enable signals) that can be asserted by any of several devices.
Bus Hold
Each Arria GX device I/O pin provides an optional bus-hold feature.
Bus-hold circuitry can hold the signal on an I/O pin at its last-driven
state. Since the bus-hold feature holds the last-driven state of the pin until
the next input signal is present, an external pull-up or pull-down resistor
is not needed to hold a signal level when the bus is tri-stated.
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Table 2–24. Programmable Drive Strength
The Quartus II software default current setting is the maximum setting for each
I/O standard.
I/O Standard
Table
shows the possible settings for I/O standards with drive
2–24:
I
Setting (mA) for Column
OH
24, 20, 16, 12, 8, 4
24, 20, 16, 12, 8, 4
/ I
12, 10, 8, 6, 4, 2
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
20, 18, 16, 8
16, 12, 8, 4
24, 20, 16
20, 18, 16
20, 18, 16
Current Strength
8, 6, 4, 2
I/O Pins
12, 8
Arria GX Device Handbook, Volume 1
Note (1)
I
Setting (mA) for Row I/O
OH
Arria GX Architecture
/ I
OL
12, 10, 8, 6, 4
10, 8, 6, 4
Current Strength
8, 6, 4, 2
12, 8, 4
12, 8, 4
8, 6, 4
12, 8
Pins
8, 4
4, 2
16
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