ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 27

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
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deactivated, the rx_syncstatus signal acts as a re-synchronization
signal to signify that the alignment pattern has been detected but not
locked on a different word boundary.
When using the synchronization state machine, the rx_syncstatus
signal indicates the link status. If the rx_syncstatus signal is high, link
synchronization is achieved. If the rx_syncstatus signal is low, link
synchronization has not yet been achieved, or there were enough code
group errors to lose synchronization.
For more information about manual alignment modes, refer to the
Arria GX Device Handbook.
The rx_patterndetect signal pulses high during a new alignment
and whenever the alignment pattern occurs on the current word
boundary.
Programmable Run Length Violation
The word aligner supports a programmable run length violation counter.
Whenever the number of the continuous ‘0’ (or ‘1’) exceeds a user
programmable value, the rx_rlv signal goes high for a minimum pulse
width of two recovered clock cycles. The maximum run values supported
are 128 UI for 8-bit serialization or 160 UI for 10-bit serialization.
Running Disparity Check
The running disparity error rx_disperr and running disparity value
rx_runningdisp are sent along with aligned data from the 8B/10B
decoder to the FPGA. You can ignore or act on the reported running
disparity value and running disparity error signals.
Bit-Slip Mode
The word aligner can operate in either pattern detection mode or in
bit-slip mode.
Arria GX Device Handbook, Volume 1
Arria GX Architecture
2–19