ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 28

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
2–20
Arria GX Device Handbook, Volume 1
The Bit-slip mode provides the option to manually shift the word
boundary through the FPGA. This feature is useful for:
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The word aligner outputs a word boundary as it is received from the
analog receiver after reset. You can examine the word and search its
boundary in the FPGA. To do so, assert the rx_bitslip signal. The
rx_bitslip signal should be toggled and held constant for at least two
FPGA clock cycles.
For every rising edge of the rx_bitslip signal, the current word
boundary is slipped by one bit. Every time a bit is slipped, the bit received
earliest is lost. If bit slipping shifts a complete round of bus width, the
word boundary is back to the original boundary.
The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals
of all four channels within a transceiver. The channel aligner follows the
IEEE 802.3ae, clause 48 specification for channel bonding.
The channel aligner is a 16-word FIFO buffer with a state machine
controlling the channel bonding process. The state machine looks for an
/A/ (/K28.3/) in each channel and aligns all the /A/ code groups in the
transceiver. When four columns of /A/ (denoted by //A//) are
detected, the rx_channelaligned signal goes high, signifying that all
the channels in the transceiver have been aligned. The reception of four
consecutive misaligned /A/ code groups restarts the channel alignment
sequence and sends the rx_channelaligned signal low.
Longer synchronization patterns than the pattern detector can
accommodate
Scrambled data stream
Input stream consisting of over-sampled data
Altera Corporation
May 2008