ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 170

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Operating Conditions
4–16
Arria GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Functional
BASIC
Single
Width
Table 4–9. PCS Latency (Part 2 of 2)
Mode
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set
gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth.
Tables
Configuration
with Rate
with Rate
16/20-bit
16/20-bit
Matcher
Matcher
Matcher
Matcher
channel
channel
channel
channel
8/10-bit
8/10-bit
without
without
width;
width;
width;
width;
Rate
Rate
4–9:
Aligner
2-2.5
2-2.5
Word
4-5
4-5
Deskew
FIFO
-
-
-
-
Note (1)
5.5-6.5
Matcher
11-13
Rate
(3)
-
-
Decoder
8B/10B
0.5
0.5
1
1
Receiver PCS Latency
Receiver
Machine
State
-
-
-
-
serializer
Byte
De-
1
1
1
1
Order
Byte
1
1
1
1
Altera Corporation
Receiver
Phase
Comp
FIFO
1-2
1-2
1-2
1-2
May 2008
Receiver
PIPE
1
-
-
-
19-23
11-14
8-10
Sum
6-7
(2)