ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 55

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–34. ALM in Arithmetic Mode
Altera Corporation
May 2008
datae0
datae1
dataf0
dataf1
datab
dataa
datad
datac
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder’s carry output along with combinational logic outputs.
In this operation, adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in
equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal will be ‘1.’ The carry_out
signal is fed to an adder where it drives out to the LAB local interconnect.
It then feeds to the LAB-wide syncload signal. When asserted,
syncload selects the syncdata input. In this case, the data ‘Y’ drives
the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’
the syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
carry_out
carry_in
adder0
adder1
D
D
reg0
reg1
Q
Q
Arria GX Device Handbook, Volume 1
To general or
To general or
To general or
local routing
To general or
local routing
local routing
local routing
Figure
Arria GX Architecture
2–35. The
2–47