ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 36

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback
2–28
Arria GX Device Handbook, Volume 1
FPGA
Interface
Logic
Array
PIPE
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
FIFO
RX Phase
Compe-
nsation
FIFO
TX Phase
Compe-
nsation
FIFO
Serializer
Byte
Figure 2–20
mode.
PCI Express (PIPE) Reverse Parallel Loopback
Figure 2–21
loopback. The reverse parallel loopback configuration is compliant with
the PCI Express (PIPE) specification and is available only on PCI Express
(PIPE) mode.
You can dynamically put the PCI Express (PIPE) mode transceiver in
reverse parallel loopback by controlling the tx_detectrxloopback
port instantiated in the MegaWizard Plug-In Manager. A high on the
Serializer
Serializer
Byte
De-
Byte
20
serializer
Byte
De-
Encoder
8B/10B
show the Arria GX block in reverse serial pre-CDR loopback
shows the data path for PCI Express (PIPE) reverse parallel
Encoder
Decoder
8B/10B
8B/10B
Decoder
8B/10B
Generator
PRBS
BIST
Parallel Loopback
PIPE Reverse
Match
FIFO
Rate
Match
FIFO
Rate
Transmitter PCS
Receiver PCS
Deskew
FIFO
Aligner
PRBS
Verify
Word
BIST
Aligner
Word
Receiver PMA
Serializer
Analog Receiver and
Transmitter Logic
Serializer
serializer
De-
Transmitter PMA
De-
Altera Corporation
Serializer
Recovery
Reverse
Serial
Pre-CDR
Loopback
Clock
Recovery
Unit
Clock
Unit
May 2008