ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 284

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

High-Speed I/O Specifications
High-Speed I/O
Specifications
4–130
Arria GX Device Handbook, Volume 1
t
f
J
W
t
t
Timing unit interval (TUI)
f
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
t
t
C
H S C L K
R I S E
F A L L
H S D R
H S D R D P A
DUTY
L O C K
Table 4–114. High-Speed Timing Specifications and Definitions
High-Speed Timing Specifications
Table 4–114
1.2-V HSTL
LVPECL
Table 4–113. Maximum DCD for DDIO Output on Column I/O Pins With PLL
in the Clock Path (Part 2 of 2)
Maximum DCD (ps) for Column
DDIO Output I/O Standard
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Maximum/minimum LVDS data transfer rate (f
Maximum/minimum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges,
including t
measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
provides high-speed timing specifications definitions.
C O
variation and clock skew. The clock is included in the TCCS
C
/w).
Definitions
Arria GX Devices (PLL Output
-6 Speed Grade
Feeding DDIO)
155
180
H S D R
H S D R D PA
= 1/TUI), non-DPA.
Altera Corporation
= 1/TUI), DPA.
May 2008
Unit
ps
ps