ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 120

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
Figure 2–76. Output Timing Diagram in DDR Mode
2–112
Arria GX Device Handbook, Volume 1
EP1AGX20
EP1AGX35
EP1AGX50/60 484-pin FineLine BGA
Table 2–23. DQS and DQ Bus Mode Support (Part 1 of 2)
Device
From Internal
Registers
DDR output
484-pin FineLine BGA
484-pin FineLine BGA
780-pin FineLine BGA
780-pin FineLine BGA
1,152-pin FineLine BGA
CLK
Package
The Arria GX IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. The negative-edge-clocked
OE register holds the OE signal inactive until the falling edge of the clock
to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Arria GX devices also
have dedicated phase-shift circuitry for interfacing with external memory
interfaces, including DDR, DDR2 SDRAM, and SDR SDRAM. In every
Arria GX device, the I/O banks at the top (Banks 3 and 4) and bottom
(Banks 7 and 8) of the device support DQ and DQS signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36.
of DQ and DQS buses that are supported per device.
A1
B1
B1
A1
B2
A2
B2
Number of
×4 Groups
A2
18
18
36
2
2
2
A3
B3
B3
Note (1)
A3
×8/×9 Groups
Number of
A4
B4
B4
18
0
0
8
0
8
A4
Table 2–23
Number of
×16/×18
Groups
0
0
4
0
4
8
shows the number
Altera Corporation
Number of
May 2008
×32/×36
Groups
0
0
0
0
0
4