ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 47

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ep1agx50d

Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Figure 2–28. High-Level Block Diagram of the Arria GX ALM
Altera Corporation
May 2008
datae0
datae1
dataf0
dataf1
dataa
datab
datac
datad
Combinational
Logic
to the two ALUTs, one ALM can implement various combinations of two
functions. This adaptability allows the ALM to be completely backward-
compatible with four-input LUT architectures. One ALM can also
implement any function of up to six inputs and certain seven-input
functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a
shared arithmetic chain, and a register chain. Through these dedicated
resources, the ALM can efficiently implement various arithmetic
functions and shift registers. Each ALM drives all types of interconnects:
local, row, column, carry chain, shared arithmetic chain, register chain,
and direct link interconnects.
diagram of the Arria GX ALM while
of all the connections in the ALM.
shared_arith_out
shared_arith_in
carry_out
carry_in
adder0
adder1
reg_chain_out
reg_chain_in
Figure 2–28
Arria GX Device Handbook, Volume 1
Figure 2–29
D
D
shows a high-level block
reg0
reg1
Q
Q
shows a detailed view
Arria GX Architecture
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–39

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