ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 53

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
using the bottom set of output drivers. The Quartus II Compiler
automatically selects the inputs to the LUT. Asynchronous load data for
the register comes from the datae or dataf input of the ALM. ALMs in
normal mode support register packing.
Figure 2–32. Six-Input Function in Normal Mode
Notes to
(1)
(2)
Extended LUT Mode
Extended LUT mode is used to implement a specific set of seven-input
functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-
input functions sharing four inputs.
supported seven-input functions utilizing extended LUT mode. In this
mode, if the seven-input function is unregistered, the unused eighth
input is available for register packing. Functions that fit into the template
shown in
appear in designs as “if-else” statements in Verilog HDL or VHDL code.
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(2)
If datae1 and dataf1 are used as inputs to the six-input function, datae0 and
dataf0 are available for register packing.
The dataf1 input is available for register packing only if the six-input function is
un-registered.
These inputs are available for register packing.
Figure
Figure 2–33
2–32:
6-Input
LUT
occur naturally in designs. These functions often
Figure 2–33
Arria GX Device Handbook, Volume 1
Notes
D
D
reg0
reg1
shows the template of
Q
Q
(1),
Arria GX Architecture
(2)
To general or
local routing
To general or
local routing
To general or
local routing
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