ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 113

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–70. Signal Path Through the I/O Block
Altera Corporation
May 2008
From Logic
To Logic
Array
Array
Row or Column
io_dataouta
io_dataoutb
io_clk[7..0]
io_dataina
io_datainb
io_ce_out
io_ce_in
io_aclr
io_sclr
io_clk
io_oe
There are 32 control and data signals that feed each row or column I/O
block. These control and data signals are driven from the logic array. The
row or column IOE clocks, io_clk[7..0], provide a dedicated routing
resource for low-skew, high-speed clocks. I/O clocks are generated from
global or regional clocks (refer to
page
Figure 2–70
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset,
clk_in, and clk_out.
selection.
2–80).
Selection
Control
Signal
illustrates the signal paths through the I/O block.
oe
ce_in
ce_out
aclr/apreset
sclr/spreset
clk_in
clk_out
Figure 2–71
To Other
IOEs
“PLLs and Clock Networks” on
illustrates the control signal
Arria GX Device Handbook, Volume 1
IOE
Arria GX Architecture
2–105