ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 108

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
Figure 2–66. Arria GX Device Fast PLL
Notes to
(1)
(2)
(3)
(4)
I/O Structure
2–100
Arria GX Device Handbook, Volume 1
Clock
Input
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES)
circuitry. Arria GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support
mode.
This signal is a differential I/O SERDES control signal.
Arria GX fast PLLs only support manual clock switchover.
Figure
Global or
regional clock (1)
Global or
regional clock (1)
4
2–66:
f
Shaded Portions of the
PLL are Reconfigurable
Circuitry (4)
Switchover
Clock
For more information about enhanced and fast PLLs, refer to the
Arria GX Devices
Refer to
for more information about high-speed differential I/O support.
The Arria GX IOEs provide many features, including:
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■
■
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■
■
■
■
■
■
■
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■
÷n
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip termination for differential standards
Programmable pull-up during configuration
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
Frequency
Detector
Phase
“High-Speed Differential I/O with DPA Support” on page 2–124
PFD
Charge
Pump
chapter in volume 2 of the Arria GX Device Handbook.
Loop
Filter
÷m
VCO
VCO Phase Selection
Selectable at each PLL
Output Port
÷k
8
Post-Scale
Counters
÷c0
÷c1
÷c2
÷c3
4
Altera Corporation
4
8
8
diffioclk0
load_en0
load_en1
diffioclk1
Global clocks
Regional clocks
to DPA block
May 2008
PLLs in
(2)
(3)
(3)
(2)