ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 191

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Table 4–44. Output Timing Measurement Methodology for Output Pins
(5)
(4)
(4)
(4)
(5)
(4)
I/O Standard
(4)
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1)
(2)
(3)
R
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
V
S
25
25
25
25
25
CCPD
CCINT
(
Ω
Output
Buffer
Figure
V
)
GND
CCIO
is 3.085 V unless otherwise specified.
is 1.12 V unless otherwise specified.
R
4–7:
D
(
Output
Ω
Loading and Termination
)
V
MEAS
R
T
50
25
50
25
50
25
50
25
50
(
Ω
)
R
S
V
CCIO
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
GND
V
TT
R
C
(V)
Arria GX Device Handbook, Volume 1
T
L
Notes
DC and Switching Characteristics
V
1.123
1.123
0.790
0.790
0.790
0.790
0.648
0.648
1.123
TT
(V)
(1), (2),
C
L
10
10
(pF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(3)
Output
Output
(Part 1 of 2)
Measurement
p
n
V
1.5675
1.5675
1.1875
0.7125
1.1625
1.1625
0.6875
0.6875
1.1625
MEAS
0.855
1.485
1.485
0.570
R
Point
0.83
0.83
0.83
0.83
D
(V)
4–37