ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 46

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Adaptive Logic Modules
Figure 2–27. LAB-Wide Control Signals
Adaptive Logic
Modules
2–38
Arria GX Device Handbook, Volume 1
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
6
6
load acts as a preset when the asynchronous load data input is tied high.
When the asynchronous load/preset signal is used, the labclkena0
signal is no longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack interconnects have inherently
low skew. This low skew allows the MultiTrack interconnects to
distribute clock and control signals in addition to data.
Figure 2–27
The basic building block of logic in the Arria GX architecture is the ALM.
The ALM provides advanced features with efficient logic utilization. Each
ALM contains a variety of look-up table (LUT)-based resources that can
be divided between two adaptive LUTs (ALUTs). With up to eight inputs
6
labclk0
clock signals per LAB.
There are two unique
shows the LAB control signal generation circuit.
or asyncload
or labpreset
labclkena0
labclk1
labclkena1
labclk2
labclkena2
syncload
Altera Corporation
labclr0
May 2008
labclr1
synclr