ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 92

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

PLLs and Clock Networks
Figure 2–57. Hierarchical Clock Networks Per Quadrant
2–84
Arria GX Device Handbook, Volume 1
Regional Clock Network [7..0]
Global Clock Network [15..0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
Figures 2–58
clock, regional clock, and PLL external clock output, respectively.
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
through
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [23..0]
2–60
show the clock control block for the global
Column I/O Cell
IO_CLK[7..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
Altera Corporation
May 2008