mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 100

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

C4M/C2M (when operating in Generic backplane mode) with the output of an fnxi counter clocked by the Network
Clock Divider circuit examined in Section 4.7.2.3 on page 98. The result of the comparison is stored in a FIFO, for
eventual transmission of the RTS nibbles to the TX_SAR. Underrun and overflow detection are provided on the
Transmit SRTS FIFO via status bits in CPU-accessible registers. The circuit operates in essentially the same way in
the reassembly direction, except that the local clock rate is determined by the clock at the output of the port’s
internal PLL, PLLCLK. As well, in the reassembly direction, data is sent to the Receive SRTS sub-module rather
than being sent to the Transmit SRTS FIFO. Figure 39 shows how the circuit is implemented.
UDT Operation
The STiCLK or PLLCLK signal for each port (C4M/C2M isn’t used, because it is an SDT-mode signal) is divided
down to generate a clock, RTS_CLK. This clock has the same frequency as a cycle of RTS. Since one RTS value is
transmitted over the course of 8 cells, the division is by 3008, the number of payload bits transmitted within one
RTS period (8 cells containing 47 payload bytes). Every time RTS_CLK pulses, the current value of the appropriate
fnxi counter is stored in a FIFO. A value from the FIFO is transmitted to the TX_SAR cell header generator circuit
once every 8-cell sequence.
SDT Operation
In some cases, the STiCLK/C4M/C2M/PLLCLK input clock requires modification prior to being used in the RTS
generator circuit described above. The line rate clock (i.e., 2.048 MHz for DS1/E1/backplane) which is input to the
MT90528 represents the rate at which bits are being received on a particular port. In SDT mode, the line rate only
represents the bit rate of a VC if the entire stream (e.g., 32 channels in ST-BUS mode) is transmitted in a single VC.
For all other cases (i.e., for N-channel VCs, where N is less than the maximum number of channels on a port), the
RTS-generating clock must represent the bit rate of a particular VC. This bit rate is determined by the number of
channels transmitted within a VC. Figure 40 below shows the line rate clock being passed through the gapping
divider circuitry to generate a bit-rate clock.
Note 2: PLLCLK is used when receiving RTS (clock recovery) or to dejitter the clock before generating RTS.
Note 1: The 4-bit fnxi counters are only required once per device. All the other circuitry is instantiated on a per-port basis.
C4M/C2M
PLLCLK
STiCLK
RTSSEL
Mux
Figure 40)
Circuitry
Gapping
sync_clk
(see
SDT/UDT
Mux
2:1
Network Clock
Divider Circuit)
fnxi counters
(generated by
Figure 39 - Transmit SRTS Sub-module
Clock Management Module
(/ 3008 or
SDT/UDT
Circuitry
Divider
/ 3000)
Zarlink Semiconductor Inc.
MT90528
fnxi2_count<3:0>
fnxi1_count<3:0>
100
To port’s PLL for RX
SRTS Recovery
Mux
2:1
RTS_int<3:0>
RTS_CLK
FNXISEL
4
New FIFO Entry
5-deep 4-bit
FIFO
4
Data Sheet
Transmit RTS
TX_SAR
Module
Value