mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 25

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

E4, D2, C1,
A2, B3, C3,
C4, A3, B4,
C5, A4, D6,
E7, B5, A5,
C6, D7, B6,
Ball Pin #
D3, D4
D5
C2
A1
A6
B1
B2
UTO_OUT_ADD[4
UTO_OUT_DATA[
UTO_OUT_ENBA
UTO_OUT_CLAV
UTO_OUT_SOC
UTO_OUT_CLK
UTO_OUT_PAR
ATM_ ENBPHY
TM_ CLAVPHY
Pin Name
15:0]
:0]
I/O
I/O 3.3 V CMOS
O
O
O
O
I
I
3.3 V, 12 mA
3.3 V, 12 mA
3.3 V, 12 mA
3.3 V, 16 mA
3.3 V CMOS
3.3 V CMOS
PD / 24 mA
Table 4 - UTOPIA Bus Pins
Type
PD
PD
Zarlink Semiconductor Inc.
MT90528
Synchronization clock for data transfer on
clock can be output from an internal divider (equal to MCLK/2) or
input from an external source. (TxClk when the MT90528 is in
ATM mode; RxClk when the MT90528 is in PHY mode.)
Multi-PHY Address signals. These address inputs are used to poll
the MT90528, and to select the next MPHY device to drive data
on UTO_OUT_DATA. These signals are driven from the ATM-end
to the PHY-end, and only used when the MT90528 is in PHY
mode. (Inactive when the MT90528 is in ATM mode; RxAddr
when the MT90528 is in PHY mode.)
16-bit UTOPIA output data bus for cell-based data. When in 8-bit
mode, only bits [7:0] are active. In Level 2 operation, this bus is
tristated between cell transmissions. (TxData when the MT90528
is in ATM mode; RxData when in PHY mode.)
Odd parity bit over UTO_OUT_DATA[15:0]. When in 8-bit mode,
odd parity bit over UTO_OUT_DATA[7:0]. In Level 2 operation,
this signal is tristated between cell transmissions. (TxPrty when
the MT90528 is in ATM mode; RxPrty when in PHY mode.)
Start of Cell for UTO_OUT_DATA. Active HIGH output signal indi-
cating the first word/byte of the cell being transmitted. In Level 2
operation, this signal is tristated between cell transmissions.
(TxSOC when the MT90528 is in ATM mode; RxSOC when in
PHY mode.)
Handshake input for UTO_OUT_DATA.
When the MT90528 is in ATM mode, this input is TxClav, indicat-
ing that the PHY-end can accept a complete cell on
UTO_OUT_DATA.
When the MT90528 is in PHY mode, this input is RxEnb*, indicat-
ing that the ATM-end will begin to sample UTO_OUT_DATA and
UTO_OUT_SOC at the end of the next clock cycle.
Handshake output for UTO_OUT_DATA.
When the MT90528 is in ATM mode, this output is TxEnb*, indi-
cating that the data on UTO_OUT_DATA is valid.
When the MT90528 is in PHY mode, this output is RxClav, indi-
cating that the MT90528 has a complete cell ready to output on
UTO_OUT_DATA.
25
Description
UTO_OUT_DATA
Data Sheet
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