mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 48

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Inactive Channels
A recommended solution would be to open a dummy receive VC(s) containing up to 128 inactive channels. This will
increase the prospect that active channels (x) will not mis-report underrun as more (x+4) channels will be active.
The procedure would be as follows
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4.3.2.4
There are two loopback modes implemented in the TDM module.
4.3.2.5
The first loopback mode is TDM low-latency loopback, and is enabled by setting the TDM_LOW_LATENCY_LPBK
bit in a port’s TDM Control Register 1. When this bit is set, the TDM data coming in on DSTi is directly output on the
DSTo output line of the same TDM port, with a delay through the device of about two TDM clock cycles.
TDM Circular Buffer Loopback (SDT Mode)
The second loopback is performed at the Circular Buffer level. It can only be used in SDT mode and it is selected by
setting the TDM_CIR_BUF_LPBK bit in a port’s TDM Control Register 1. In this loopback mode, the TDM SDT
reassembly process uses the TDM_SEGMEN_BASE_ADD (in the per-port TDM Control Register 2) as the base
address for the SDT Reassembly Circular Buffers in external memory. This loopback mode can be used to:
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To determine which channels to loop back and their order, the TDM reassembly process reads the TDM SDT
Reassembly Control Structure (refer to Figure 13 on page 46), which should be programmed in the following
manner:
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4.4
The MT90528’s UTOPIA interface is compliant with the ATM Forum Level 2 specification for the UTOPIA interface
(af-phy-0039.000). The Level 2 specification is backwards-compatible with the Level 1 specification (af-phy-
0017.000); therefore, the MT90528 interface also supports Level 1 applications. The UTOPIA interface is capable
of emulating either a PHY device or an ATM device.
VC, re-open the dummy receive VC(s) (with less channels), unmask the TDM interrupts
To close a valid receive VC - mask TDM interrupts, close the valid receive VC, close the dummy receive
VC(s), re-open the dummy receive VC(s) (with more channels), unmask the TDM interrupts
loop back an entire stream
loop back certain channels while tristating others
switch the data between various channels (within the same port)
V - The valid bits should be set for those channels which should be output on DSTo/CSTo. If the valid bit for
a channel is not set, the output channel is tristated.
SU, I, and PU bits - These bits should be cleared.
Reassembly Circular Buffer Address bits -
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bit<0> - This bit must be set to ‘1’ (the SDT Segmentation Circular Buffers onto which the SDT Reassembly
Circular Buffers are mapped always contain 64 entries).
To open a valid receive VC - mask TDM interrupts, close the dummy receive VC(s), open the valid receive
UTOPIA Interface Module
bits<9:6> - These bits should be cleared as they are not used in loopback mode.
bits<5:1> - These five bits identify the input channel whose data is being output on the timeslot
associated with this entry.
TDM Loopback
TDM Low-Latency Loopback
Zarlink Semiconductor Inc.
MT90528
48
Data Sheet