mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 105

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Modes of Operation (PLL_INPUT_SEL bits)
The PLL has four major modes of operation which are configured on a per-port basis via the PLL_INPUT_SEL bits
in the Clocking Configuration Registers. The four modes are, briefly, as follows:
•
•
•
•
Note that the UDT RX_SAR and SDT RX_SAR Reassembly Control Structures must be configured appropriately if
either Adaptive or SRTS Clock Recovery methods are to be used. For more details, refer to the UDT RX_SAR and
SDT RX_SAR module descriptions in Section 4.6.1, “UDT RX_SAR and SDT RX_SAR Modules” earlier in this
document.
Line-clocking mode: Synchronize to a 1.544 MHz, 2.048 MHz, or 4.096 MHz clock input to the chip on the
port’s corresponding STiCLK input line. Generate an outgoing clock with the appropriate frequency. The
outgoing service clock (1.544 MHz, 2.048 MHz, or 4.096 MHz) is phase-locked to the input clock. This mode
of operation may be used to “clean up” a jittery input clock. In line-clocking mode, the maximum locking time
is about 15 seconds.
SRTS mode: Synchronize to the incoming RTS nibbles (time stamps). Generate a 1.544 MHz, 2.048 MHz, or
4.096 MHz clock. The proper service output clock is fed into the per-port SRTS generator (outlined in
Section 4.7.2.4, “Transmit SRTS Circuit Sub-module,” on page 99) to generate a local RTS value that is
compared with subsequent received RTS values. In SRTS mode, the maximum locking time is
approximately 100 seconds.
Network mode: Similar to line-clocking mode, but the input clock is an 8 kHz clock (coming either directly
from the PHY_CLK pin or from a divided down version of a 19.44MHz clock input at the PHY_CLK pin). The
8 kHz clock is sourced from the Clock Management module, as explained in Section 4.7.2.3, “Network Clock
Divider Circuit,” on page 98. The output clock (1.544 MHz, 2.048 MHz, or 4.096 MHz) is synchronous and
phase-locked to the 8 kHz input clock. In network mode, the maximum locking time is about 40 seconds.
Adaptive mode: Synchronize to the incoming cell stream by monitoring the fill level of a VC’s Reassembly
Circular Buffers. The PLL receives a phaseword from the UDT RX_SAR or SDT RX_SAR. A clock rate of
approximately 1.544 MHz, 2.048 MHz, or 4.096 MHz is generated, depending upon the PLL_FREQ_SEL
bits.
Phaseword
Received
Clock
RTS
* - outside PLL module
Detector
Phase
Generator
Figure 43 - Block Diagram of the Digital PLL Module
DCO_DIFF
SRTS
*
Filter implemented in
software (via CPU)
Loop
Filter
Zarlink Semiconductor Inc.
fnxi
MT90528
105
DCO
Network mode
Divider
8kHz_PLL
Mux
2:1
frequency
offset
output
clock
RTS out
Data Sheet