mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 171

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

7.2.3
DSTi/DSTo
for DS1: n=192
for E1: n=255
STiCLK/SToCLK
for DS1: 1.544 MHz
for E1: 2.048 MHz
STiMF/SToMF or F0
(See Note)
STiCLK/SToCLK
or C4M/C2M
1.544 MHz
Note: Due to the use of Generic mode, clock and frame pulse polarity are programmable. Data can be sampled/driven out
either on the falling edge or the rising edge of the clock. The frame pulse can have either positive or negative polarity.
DSTi/DSTo
STiMF/SToMF or F0
(ST-BUS)
STiCLK/SToCLK
or C4M/C2M
4.096 MHz (ST-BUS only)
STiMF/SToMF or F0
(Generic - see Note)
STiCLK/SToCLK
or C4M/C2M
2.048 MHz (Generic only)
DSTi/DSTo
Note: In Generic format, both clock polarity and frame pulse polarity are programmable. Data can be sampled/driven out
either on the falling edge or the rising edge of the clock. The frame pulse can have either positive or negative polarity.
Note: Clock polarity is programmable. Data can be sampled/driven out either on the falling edge or the rising edge of the
clock.
TDM Interface
Figure 54 - Nominal SDT Mode Timing Diagram - Generic and ST-BUS DS1 or E1 (2.048 Mbps)
Figure 53 - Nominal UDT Mode Timing Diagram - DS1 (1.544 Mbps) and E1 (2.048 Mbps)
Figure 55 - Nominal SDT Mode Timing Diagram - Generic DS1 (1.544 Mbps)
Timeslot 24
Bit 1
Timeslot 31
Bit n-1
Bit 0
Timeslot 24
Bit 0
Bit n
Zarlink Semiconductor Inc.
MT90528
Framing
Bit
Timeslot 0
Bit 0
Bit 7
171
Timeslot 0
Bit 7
Bit 1
Timeslot 0
Bit 6
Bit 2
Timeslot 0
Bit 6
Timeslot 0
Bit 5
Bit 3
Timeslot 0
Bit 4
Timeslot 0
Bit 4
Bit 5
Timeslot 0
Bit 3
Bit 5
Data Sheet