mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 103

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

In general, the Receive SRTS sub-module simply holds a FIFO of RTS values which were extracted from received
cells by either the UDT RX_SAR or the SDT RX_SAR. The RTS value transmitted from the RX_SAR to the Clock
Management module is actually 5 bits long, rather than a 4-bit RTS nibble. The extra bit provides error-detection to
the internal digital PLL. In the event of a lost cell or unrecoverable error being detected by the RX_SAR, the MSB of
the received RTS value is set to 1. The internal digital PLL detects this error and discards the current RTS value
from both the RX_SAR and the local Transmit SRTS circuit. More detail about this error protection scheme can be
found in Section , “RTS Reception for SRTS Clock Recovery,” on page 88. When the port’s PLL requests a new
RTS value, the Receive SRTS sub-module sends the required nibble and validity indicator to the PLL. The actual
generation of the output clock based on the RTS nibbles is performed within the digital PLL. Refer to
Section 4.7.2.7 on page 104 for a detailed explanation of the digital PLL design.
Note that underrun and overflow detection is provided on the Receive SRTS FIFO. Two register bits are provided to
inform the user that underruns or overflows have been detected. If there were not enough RTS values placed into
the Receive RTS FIFO by the UDT RX_SAR or the SDT RX_SAR (e.g., because of multiple consecutive sequence
number errors, as explained above), the FIFO would eventually underrun. However, the Receive SRTS FIFO
underrun protection puts the PLL into holdover mode automatically. Once an entry has been read from the Receive
SRTS FIFO by the PLL, the data at that location in the FIFO is overwritten, marking the data as “invalid”. Although
during an underrun event, new RTS values are not being placed into the Receive SRTS FIFO, the PLL continues to
read RTS values from the FIFO. Eventually, the PLL will read out previously-read data. The reception of these now-
invalid RTS values forces the PLL into automatic holdover mode.
4.7.2.6
The adaptive clock recovery technique is recommended in ITU-T I.363.1, but not standardized. The general
approach is to monitor the fill-level of the received data buffers to determine the clocking rate. If the fill-level is
above average, the local clock must be operating at a lower rate than the remote clock. As such, the local clock
frequency should be increased so that the buffer is emptied more quickly. On the other hand, if the fill-level
measured is below average, the buffer is being emptied too quickly and the local clock rate should be decreased to
match the rate of the remote clock.
Within the Clock Management module, the adaptive clock recovery technique is implemented via an internal PLL,
as shown in Figure 42. Each port has its own PLL, which is the same as the one outlined for SRTS operation in the
Adaptive Clock Recovery Circuit
Received RTS Value
(4 bits plus validity
RX_SAR
Module
indicator)
5
5-deep 5-bit
Figure 41 - Receive SRTS Sub-module
FIFO
Zarlink Semiconductor Inc.
MT90528
Clock Management Module
FIFO_RTS<4:0>
(generated by Transmit
SRTS circuit - indi-
cates new value has
been generated)
103
RTS_CLK
5
Digital PLL (refer
Section 4.7.2.7
for details)
to
(generated by Transmit
SRTS circuit prior to
storage in FIFO)
4
RTS_int<3:0>
PLLCLK (SRTS)
TDM Sub-Module”
Clocking Circuit”
To “Interface to
Multiplexers &
“Synchronous
Multiplexers
Data Sheet