mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 149

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

6.2.8
Address: 5000 (Hex)
Label: CMCR
Reset Value: 0001 (Hex)
SLV_N_MSTR
FNXI1_RATE
8_KHZ_SEL
EXT_N_INT
F0_MODE
Label
Clock Management Module
Position
4:2
8:6
Bit
0
1
5
Table 75 - Clock Management Configuration Register
Type
R/W
R/W
R/W
R/W
R/W
Slave/Master.
When set, the signals F0 and C4M_C2M are sourced from the TDM backplane (inputs).
When cleared, the MT90528 generates these signals (outputs).
When the MT90528 is not operating in backplane mode, this bit should be set to 1
(i.e., slave mode). Furthermore, if operating in backplane mode, this bit should
only be cleared if the user wishes the MT90528 to control the F0 and C4M_C2M
backplane signals.
External/Internal.
When set, the common clock and the “master” C4M_C2M and F0 signals are generated
from the clock input to the MT90528 at TDM_CLK (this is usually sourced from an external
PLL).
When cleared and if in master mode, the C4M_C2M and F0 signals are generated from an
internal version of the output signal PRI_REF.
Frame Pulse Format Selector.
F0_MODE<0> - Frame Pulse Polarity (used only in Generic mode):
F0_MODE<1> - Frame Pulse Trigger Edge (used only in Generic mode):
F0_MODE<2> - Frame Pulse Format:
Internal 8 kHz clock source.
Used to select the origin of the 8 kHz clock source used by the internal PLLs.
When set, the 8 kHz clock is generated as a divided-down version of the 19.44 MHz clock
input to the MT90528 at PHY_CLK.
When cleared, an 8 kHz clock is expected to be input directly at PHY_CLK.
FNXI Rate Selector 1. (See Notes 1 and 2)
These bits are used to select the rate of the FNXI clock (#1) from which outgoing RTS val-
ues will be generated, and to which incoming RTS values will be compared:
“000” = 75,937.5 Hz
“001” = 151,875 Hz
“010” = 303,750 Hz
“011” = 607,500 Hz
“100” = 1.215 MHz
“101” = 2.43 MHz (UDT rate)
“110” = 4.86 MHz
“111” = 9.72 MHz.
‘0’ = Negative polarity
‘1’ = Positive polarity.
‘0’ = Negative-edge trigger
‘1’ = Positive-edge trigger.
‘0’ = Generic
‘1’ = ST-BUS.
Zarlink Semiconductor Inc.
MT90528
149
Description
Data Sheet