mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 153

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 5200 + p*10 (Hex)
Label: CCR_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Address: 5202 + p*10 (Hex)
Label: CPAR_Pp (where p represents the port number)
Reset Value: 8000 (Hex)
Note: The reset value of this register can only be read as 8000h if the corresponding PLL is disabled (bit<0> cleared in the PLL Enable
Register, located at address 5208h+p*10h).
PHASE_LIMITER
PLL_INPUT_SEL
PHASE_ACCUM
VC_CHANNELS
Reserved
Label
Label
Position
Position
15:11
14:11
10:9
10:0
Table 78 - Clocking Phase Accumulator Register (one per port)
Bit
Bit
15
Table 77 - Clocking Configuration Register (one per port)
Type
Type
R/W
R/W
R/O
R/O
R/O
PLL input mode.
These bits define the input used to generate the PLL’s output clock.
“00” = Line Clocking mode; input is from the port’s STiCLK (can also be used to dejitter the
clock for timestamp generation; see Figure 39 on page 100 for an illustration).
“01” = SRTS mode; input is a digital Synchronous Residual Time Stamp stream from the
RX_SAR.
“10” = Network mode; input is the 8 kHz network reference (derived from PHY_CLK pin;
see bit<5> of the Clock Management Configuration Register at 5000h).
“11” = Adaptive mode; input is determined by the buffer-fill-level from the RX_SAR.
Number of Channels in VC.
This field is used when generating or receiving RTS nibbles in SDT mode. It indicates the
number of channels in the VC which is carrying timing information for the port. The field
must be programmed by the user to be one less than the actual number of channels in the
VC (possible values = 00h to 1Fh).
Internal PLL Phase Accumulator.
This 2’s complement value represents the long-term frequency offset of the output clock
from the PLL’s centre frequency.
This value translates to the frequency offset as follows:
freq_offset = (phase_accum/3139881) * 1,544,000 Hz for DS1 mode
freq_offset = (phase_accum/4164817) * 2,048,000 Hz for E1 mode
freq_offset = (phase_accum/4164817) * 4,096,000 Hz for C4 mode.
Always reads “0000”.
Internal PLL Phase Limiter.
When cleared, indicates that the PLL is limiting its phase detector output so that the PLL
output phase changes no more than 6 ns / 125 Ps.
A change of more than 6 ns / 125 Ps typically occurs when the PLL is not locked or when
there is large jitter on the input signal of the PLL.
When PHASE_LIMITER is high for approximately 30 seconds, one can assume that the
PLL is in lock; contrarily, when PHASE_LIMITER is low for approximately 30 seconds, the
PLL is out of lock.
Zarlink Semiconductor Inc.
MT90528
153
Description
Description
Data Sheet