mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 146

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 400A (Hex)
Label: UVPM
Reset Value: 0000 (Hex)
Address: 400C (Hex)
Label: UVPME
Reset Value: 0000 (Hex)
Address: 400E (Hex)
Label: UPM
Reset Value: 0000 (Hex)
Address: 4010 (Hex)
Label: UFS
Reset Value: 0030 (Hex)
VP_MATCH_ENB
UTO_OUT_FIFO_
UTO_IN_FIFO_
MISMATCHES
VP_MATCH
LOOPBACK
Reserved
Reserved
UTOPIA_
PARITY_
RESET
RESET
Label
Label
Label
Label
Position
Position
Position
Position
15:12
15:12
11:0
11:0
15:0
Bit
Bit
Bit
Bit
0
1
2
Table 68 - UTOPIA Parity Mismatches Register
Type
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/O
Table 69 - UTOPIA FIFO Status Register
Table 67 - VP Match Enable Register
Contains match values for each of the twelve bits in the VPI (including the GFC field).
Always reads “0000”.
Each bit, when set, enables the comparison of a cell’s VPI and the corresponding
VP_MATCH bit. If a bit in this register is not set, the corresponding bit in the received cell
VPI is considered valid, regardless of the setting in the VP_MATCH field. In UNI mode,
bits<11:8> should be cleared to avoid the comparison of the GFC.
Always reads “0000”.
Contains a count of the mismatches between UTO_IN_DATA and UTO_IN_PARITY. If this
counter rolls over, the PARITY_ROLL_STATUS bit in the UTOPIA Status Register at 4012h
will be set.
When set, this bit forces the UTOPIA port into loopback mode. Data is looped from the
incoming UTOPIA bus to the outgoing UTOPIA bus, through the incoming UTOPIA FIFO
and the outgoing UTOPIA FIFO. The incoming data is filtered by the Match and Match
Enable filters before being re-transmitted.
When set, empties the outgoing UTOPIA FIFO.
When set, empties the incoming UTOPIA FIFO.
Table 66 - VP Match Register
Zarlink Semiconductor Inc.
MT90528
146
Description
Description
Description
Description
Data Sheet