mt90528ag2 Zarlink Semiconductor, mt90528ag2 Datasheet - Page 51

• Manufacturer Part Number: mt90528ag2
• Description: 28-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

4.4.1
4.4.1.1
TX UTOPIA Interface
The TX UTOPIA Interface’s primary function is to transmit ATM cells to devices outside the MT90528 chip,
according to the ATM Forum’s Level 2 UTOPIA specification. The port can operate in either ATM or PHY mode.
When the port is operating in ATM mode, it complies with the transmit portion of the ATM Forum specification; when
operating in PHY mode, it complies with the receive portion of the specification. Additionally, when operating in PHY
mode, the TX UTOPIA Interface complies with the receive sub-section of the multi-PHY section of the ATM Forum
specification.
The TX UTOPIA Interface can be configured to operate in a variety of modes. The TX UTOPIA can operate in PHY
or ATM mode, using Level 1 or Level 2 mode, with a 16-bit or 8-bit interface. The user selects between these
different modes by programming the UTOPIA Configuration Register at byte address 4000h.
When operating in 16-bit mode, the cells transmitted by the interface are 54 bytes long, whereas when operating in
8-bit mode, the cells transmitted by the interface are 53 bytes long. When operating in 8-bit mode, the upper 8 bits
of the outgoing data bus (UTO_OUT_DATA[15:8]) are not used.
When operating in Level 1 mode, the ATM Forum only specifies UTO_OUT_CLK to a maximum clock speed of 25
MHz. The user, however, is able to use the interface at speeds of up to 52 MHz, if desired.
TX UTOPIA FIFO
The main role of the TX UTOPIA FIFO is to act as a buffer between the TX_SAR and the TX UTOPIA Interface.
This buffer is necessary because it is possible for the UTOPIA bus to be halted (i.e., not able to transmit) while the
TX_SAR continues to assemble cells. This is an 8-cell deep FIFO.
TX Parity
The TX Parity sub-module generates an odd parity bit over the outgoing UTOPIA data (UTO_OUT_DATA[7:0] in 8-
bit mode, and UTO_OUT_DATA[15:0] in 16-bit mode). The resulting parity bit (UTO_OUT_PAR) is transmitted to
the external device to which the TX UTOPIA Interface is connected.
4.4.1.2
RX UTOPIA Interface
The primary function of the RX UTOPIA Interface is to receive ATM cells (in accordance with the ATM Forum’s
Level 2 UTOPIA specification), from devices which are external to the MT90528 chip. The interface can operate in
either ATM or PHY mode. When the interface is operating in ATM mode, it complies with the receive portion of the
ATM Forum specification. When the interface operates in PHY mode, it complies with the transmit portion of the
ATM Forum specification. In addition, when operating in PHY mode, the RX UTOPIA Interface complies with the
transmit sub-section of the multi-PHY section of the ATM Forum specification.
In the same manner as the TX UTOPIA Interface, the RX UTOPIA Interface can be configured to operate in a
variety of modes. It can operate in PHY or ATM mode, in Level 1 or Level 2 mode, with a 16-bit or an 8-bit interface.
The user selects between these different modes by programming the UTOPIA Configuration Register (at byte
address 4000h).
When operating in 16-bit mode, the cells received by the interface are 54 bytes long; when operating in 8-bit mode,
the cells being received are 53 bytes long. When operating in 8-bit mode, the upper 8 bits of the incoming data bus
(UTO_IN_DATA[15:8]) are not used.
Functional Description
Segmentation Direction
Reassembly Direction
Zarlink Semiconductor Inc.
MT90528
51
Data Sheet